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AR# 41246

XST - "mark_debug=true" does not stop XST from optimizing signals


The specified behavior of MARK_DEBUG is as follows:

    XST should treat this as a KEEP attribute.
    The signal that this is attached to should not be optimized away during synthesis and the resulting net(s) in the netlist should persist.
    The corresponding net(s) in the netlist should have the MARK_DEBUG property on it/them.
    No special processing is done due to the MARK_DEBUG attribute. 
    XST will optimize the design as it normally would.
    If the net(s) corresponding to the marked signal(s) is/are not optimized away during synthesis, then the corresponding net(s) in the netlist should have the MARK_DEBUG property on it/them.
    The attribute is ignored by XST.

However, in some cases signals with mark_debug set to TRUE might not show up in PlanAhead as unassigned nets because XST does not seem to stop optimizing signals with mark_debug=TRUE.


If you experience this issue in older ISE versions, please use ISE Design Suite 14.7 in which these issues have been fixed.

If you still see the issues in ISE 14.7, please try the following workarounds:

  • MARK_DEBUG is supported only in the new parser, not in the old parser.
    Please use the "-use_new_parser yes" option for Synthesis as a work-around.
    For more information on the new parser, please see (Xilinx Answer 32927).
  • The signal that you are going to connect to ChipScope may still exist in the post-synthesis netlist.
    You can try to find the signal by searching and checking connections in the Schematic in PlanAhead.
    If it is in the netlist, you can then manually mark it as debug.
  • Add a temporary load (i.e. a register) for the loadless signal you are going to mark as debug and then apply a keep attribute to the temporary load.
    In this way, the signal with mark_debug may be preserved.

AR# 41246
Date 02/23/2015
Status Active
Type Known Issues
  • ISE Design Suite - 13
  • ISE Design Suite - 14
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