Please make sure you attached TIG to the valid net.
Suppose the highlighted path in following figure is the path you would like to ignore.
You need to attach TIG to tmp1.Q rather than tmp1.D.When attached to a net, TIG pushes to the drive pin of the net. You will see the corresponding constraint in PCF as:
PIN tmp1_pins<2> = BEL "tmp1" PINNAME Q;
PIN "tmp1_pins<2>" TIG;
Review the synthesized netlist to determine the exact signal name, as the synthesis tool may change the name in HDL code for optimization.