We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41320

14.x Constraints - NET TIG does not take effect


I place aTIG constrainton a net,hoping that all paths that fan forward from that net will be ignored during timing analysis.

NET "net_name" TIG;

However, the associated path is still analyzed under PERIOD constraint.

What could be wrong?


Please make sure you attached TIG to the valid net.

Suppose the highlighted path in following figure is the path you would like to ignore.

You need to attach TIG to tmp1.Q rather than tmp1.D.When attached to a net, TIG pushes to the drive pin of the net. You will see the corresponding constraint in PCF as:

PIN tmp1_pins<2> = BEL "tmp1" PINNAME Q;
PIN "tmp1_pins<2>" TIG;

Review the synthesized netlist to determine the exact signal name, as the synthesis tool may change the name in HDL code for optimization.

AR# 41320
Date Created 04/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less