The IODELAY2 block in the Lower Power Spartan-6 -1L speed grade FPGA devices is restricted to tap 0 only.The Lower Power Spartan-6 FPGA LX Production Errata(EN168) has been updated with this issue:
NOTE: The MCB is not affected by this issue.
The IODELAY2 block must be restricted to tap 0 use only. When used on an input path, this requires the use of the FIXED delay mode (IDELAY_TYPE=FIXED) and selection of tap 0 (IDELAY_VALUE=0). IDELAY_TYPE=DEFAULT is also supported since it is equivalent to using tap 0. IDELAY_TYPE=DEFAULT is used when the IODELAY2 block is inferred by the Xilinx software tools, such as when used on an IFD registered input.When the IODELAY2 block is used on an output path, the attribute ODELAY_VALUE=0 must be used. Using tap 0 adds the delay of the IODELAY2 block itself to the I/O path, although it does not add any additional tap delay.
This issue affects all Lower Power Spartan-6 -1L speed grade devices. This errata has been in place since the start of production for the -1L speed grade.For information on using the IODELAY2 block in the standard -2/-3 speed grade devices, see (Xilinx Answer 38408).
Software and Documentation Updates:
Using the IODELAY2 for any other implementation than tap 0 results in a DRC error starting in ISE Design Suite 13.2. The DRC error is applied when using IDELAY_TYPE options VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX or DIFF_PHASE_DETECTOR, or when using IDELAY_TYPE=FIXED or ODELAY with an IDELAY_VALUE or ODELAY_VALUE greater than 0. The error message is the following:
"Error xxxx: For Speed Grade -1L, the IODELAY2 (<instance-name>) cannot support the IDELAY_TYPE set to VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX, DIFF_PHASE_DETECTOR, or FIXED (when IDELAY_VALUE or IDELAY2_VALUE are not 0), or ODELAY_VALUE not set to 0."
No IP solutions that require IODELAY2 are supported for the Lower Power Spartan-6 -1L devices.There are no user guide updates required.