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AR# 41363

13.1 EDK - Incorrect Bus2IP_Resetn polarity in user_logic.v generated by CIP Wizard

Description

When I use the Verilog version user_logic generated by CIP Wizard in 13.1 version, I cannot access the custom IP.

Solution

The 13.1 software version CIP Wizard generated user_logic.v has an incorrect polarity setting on "Bus2IP_Resetn" as below:

// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC

if ( Bus2IP_Resetn == 1 )
begin
slv_reg0 <= 0;
end

The "Bus2IP_Resetn" is active "low" according to data sheet and its name. Changing the condition of "Bus2IP_Resetn == 1" to "Bus2IP_Resetn == 0" will resolve the problem. The VHDL version user logic is correct.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39843 13.x EDK - Master Answer Record N/A N/A
AR# 41363
Date Created 03/22/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 13.1