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AR# 41383

LogiCORE IP Triple-Rate SDI v1.0 - The 13.1 Versions 1.8 and 1.9 of the Virtex-6 FPGA GTX Transceiver Wizard do not work with the Triple-Rate SDI v1.0 core

Description

The 13.1 Versions 1.8 and 1.9 of the Virtex-6 FPGA GTX Transceiver Wizard do not work with the Triple-Rate SDI v1.0 core.

Versions 1.8 and 1.9 of the Virtex-6 FPGA GTX Transceiver Wizard generate GTX wrapper files that are incompatible with the Triple-Rate SDI reference design (XAPP1075) and the Triple-Rate SDI v1.0 core available in CORE Generator in ISE 13.1 software, even when the "hd sdi" protocol template is used. The GTX wrapper files must be edited slightly in order to work with triple-rate SDI. The top level GTX wrapper generated by the wizard must be edited as indicated below.

Solution

This is a known problem that will be fixed in the Virtex-6 FPGA GTX Transceiver Wizard v1.10 in ISE 13.2 software.

You can work around this problem by making the following code changes:

In Verilog, there are three lines in the wrapper file that look like this:
assign gtx0_gtxtest_i = {11'b10000000000,gtx0_gtxtest_bit1,1'b0};
assign gtx0_txreset_i = gtx0_gtxtest_done || GTX0_TXRESET_IN;
assign gtx0_rxreset_i = gtx0_gtxtest_done || GTX0_RXRESET_IN;

The first and third lines shown above must be changed to this:
assign gtx0_gtxtest_i = {11'b10000000000,gtx0_gtxtest_bit1 | GTX0_GTXTEST_IN[1],1'b0};
assign gtx0_txreset_i = gtx0_gtxtest_done || GTX0_TXRESET_IN;
assign gtx0_rxreset_i = GTX0_RXRESET_IN;


In VHDL, these three lines look like this in the GTX wrapper file:
gtx0_gtxtest_i <= b"10000000000" & gtx0_gtxtest_bit1 & '0';
gtx0_txreset_i <= gtx0_gtxtest_done or GTX0_TXRESET_IN;
gtx0_rxreset_i <= gtx0_gtxtest_done or GTX0_RXRESET_IN;

The first and third lines must be changed to this:
gtx0_gtxtest_i <= b"10000000000" & (gtx0_gtxtest_bit1 or GTX0_GTXTEST_IN(1)) & '0';
gtx0_txreset_i <= gtx0_gtxtest_done or GTX0_TXRESET_IN;
gtx0_rxreset_i <= GTX0_RXRESET_IN;

The GTX wrapper also instantiates a module called DOUBLE_RESET, which is needed by the core. The Wizard does generate the necessary files in both Verilog and VHDL. Toimplement this module, generatethe Verilog and VHDL source from theVirtex-6 FPGA GTX Transceiver Wizard in a different directory than the Triple-Rate SDI files. Then, copy the files for theVirtex-6 FPGA GTX Transceiver Wizardmodule to the directory where the Triple-Rate SDI files are located. The DOUBLE_RESET module files can be found in the example_design directory and are called double_reset.v and double_reset.vhd.

The GTX wrapper also has an added port to provide a clock to the DOUBLE_RESET module. This port is called GTX0_DOUBLE_RESET_CLK_IN. For SDI applications, simply connect this port to the same clock that is driving the GTX0_DCLK_IN port of the GTX.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40473 LogiCORE IP Triple-Rate SDI (Serial Digital Interface) Virtex-6 - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40473 LogiCORE IP Triple-Rate SDI (Serial Digital Interface) Virtex-6 - Release Notes and Known Issues N/A N/A
AR# 41383
Date Created 03/22/2011
Last Updated 12/17/2012
Status Active
Type General Article