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AR# 41408

7-Series - How to place LVDS in a High Performance bank


In 7 Series FPGAs there are a mixture of High Performance (HP) and High Range (HR) banks. An HP bank has a maximum Vcco of 1.8V.

How do you define LVDS for an HP bank?


The IOSTANDARD for an HR bank is LVDS_25 and the IOSTANDARD for an HP is LVDS. Both LVDS and LVDS_25 are documented in the 7 Series FPGAs SelectIO User Guide UG471.

LVDS inputs are supported on an HP bank powered at Vcco=1.5V, but the swing must be below 1.7V. The internal DIFF_TERM is not supported on banks powered at 1.5V; therefore, an external 100 ohm differential termination resistor is required.

For information on voltage compatibility between LVDS in HP and HR banks, see (Xilinx Answer 40191)

AR# 41408
Date Created 03/23/2011
Last Updated 06/10/2011
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT