These errors occur in Verify UCF because the HXT columns are labeled differently than the rest of the Virtex-6 devices. MIG does not account for this difference in column labels and so generates the column constraints incorrectly. The center columns are labeled 0 and 1 as there are only two center columns, the MIG core is expecting them to be 1 and 2. While the constraints fail during Verify UCF, the design does implement in Place and Route (PAR) correctly.

For customers not using Verify UCF, no changes need to be made. However, for customers needing to modify their pin-out and use Verify UCF, the column constraints need to be modified in the generated UCF.

Here is an example:

##Site: D11 -- Bank 36
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
LOC = "OLOGIC_X1Y143";
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
LOC = "IODELAY_X1Y143";

INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
LOC = "BUFR_X1Y7";

##Site: J31 -- Bank 26
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col2.u_oserdes_rsync"
LOC = "OLOGIC_X0Y137";
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col2.u_odelay_rsync"
LOC = "IODELAY_X0Y137";

INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col2.u_bufr_rsync"
LOC = "BUFR_X0Y6";

And, its related RTL top level parameters generated as follows:

parameter C0_nDQS_COL0 = 2,
// Number of DQS groups in I/O column #1.
parameter C0_nDQS_COL1 = 0,
// Number of DQS groups in I/O column #2.
parameter C0_nDQS_COL2 = 6,
// Number of DQS groups in I/O column #3.
parameter C0_nDQS_COL3 = 0,
// Number of DQS groups in I/O column #4.
parameter C0_DQS_LOC_COL0 = 16'h0706,
// DQS groups in column #1.
parameter C0_DQS_LOC_COL1 = 0,
// DQS groups in column #2.
parameter C0_DQS_LOC_COL2 = 48'h050403020100,
// DQS groups in column #3.
parameter C0_DQS_LOC_COL3 = 0,

Modify the column number in the constraints as follows:

##Site: D11 -- Bank 36
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync"
LOC = "OLOGIC_X1Y143";
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"
LOC = "IODELAY_X1Y143";

INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync"
LOC = "BUFR_X1Y7";

##Site: J31 -- Bank 26
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
LOC = "OLOGIC_X0Y137";
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
LOC = "IODELAY_X0Y137";

INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
LOC = "BUFR_X0Y6";

The RTL top level parameters should be as follows:

parameter C0_nDQS_COL0 = 2,
// Number of DQS groups in I/O column #1.
parameter C0_nDQS_COL1 = 6,
// Number of DQS groups in I/O column #2.
parameter C0_nDQS_COL2 = 0,
// Number of DQS groups in I/O column #3.
parameter C0_nDQS_COL3 = 0,
// Number of DQS groups in I/O column #4.
parameter C0_DQS_LOC_COL0 = 16'h0706,
// DQS groups in column #1.
parameter C0_DQS_LOC_COL1 = 48'h050403020100,,
// DQS groups in column #2.
parameter C0_DQS_LOC_COL2 = 0,
// DQS groups in column #3.
parameter C0_DQS_LOC_COL3 = 0,

This difference in constraint generation will be resolved in ISE 13.2 (MIG v3.8).

03/24/11 - Initial Release