Introduction

For installation instructions for this release, see: http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements, see: http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTH Transceiver Wizard v1.8 solution. For the latest core updates, see the product page at:http://www.xilinx.com/products/intellectual-property/V6_FPGA_GTH_Transceiver_Wizard.htm

New Features

• Auto-upgrade feature to upgrade from v1.2, v1.3, v1.4, v1.5, v1.6, v1.7 to v1.8
• Added support for higher refclk Fmax (up to 700 MHz) for -2,-3 speed grade device and (up to 645 MHz) for -1 speed grade. For more information,see(Xilinx Answer 41022).

Supported Devices

The following device families are supported by the core for this release: Virtex-6 xc6vhx255t, xc6vhx380t, xc6vhx565t.

Resolved Issues

• Fixed CR
  595042 - Updated the attribute settings for Production Silicon.
  596090 - Updated the FSM in gth_tx_pcs_reset module.
  592150 - The GTH Transceiver maximum reference clock frequencyis updated to 700 MHz for -2, -3 speed grades and 645 MHz for -1 speed grade.
  594652 - Enabled 64B66B encoding for all supported line rates.
  602891 - Fixed incorrect attributes for 10G-BASE-R protocol template with None-Encoding.

Known Issues

The following are known issues for v1.8 of this core at thetime of release:

• To implement a design targeting a reference clock higher than 670 MHz (for -2, -3 speed grades) or 623 MHz (for -1 speed grade), refer to (Xilinx Answer 41022).
• TheLogiCORE IP Virtex-6 FPGA GTH Transceiver Wizard v1.6 Getting Started Guide (UG691)is not updated for this version of core.
• Limited hardware testing was done for the Virtex-6 GTH Wizard on ML627 board.
• Attribute and port settings for OTU-4 are applicable to single laneonly. The user has to integrate other OTU-4 compatible logic manually intheir design.
• For 16 and 20-bit datapath widths, multiple line rates and multiple datapath widths cannot be selected across multiple lanes.

The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide (XTP025):http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Technical Support

To obtain technical support, create a WebCase at: http://www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Other Information

This version of the wizard supports Production silicon only. Using a wrapper generated with this version of the wizard to program a CES Virtex-6 HXT device is not supported. Please use v1.7 of this Wizard to program CES devices.For guidance on how to distinguish Production from ES devices and for additional details, see(Xilinx Answer 41464).

Core Release History

Date ByVersion Description
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06/22/2011 Xilinx, Inc. 1.8(Rev1) ISE 13.2 support
04/08/2011 Xilinx, Inc. 1.8(Rev0) ISE 13.1 support
04/08/2011 Xilinx, Inc. 1.7(Rev1) ISE 13.1 support
03/01/2011 Xilinx, Inc. 1.7 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.6 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.5 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.4 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.3 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.2 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.1 Initial release
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