We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41520

Design Advisory for Spartan-6 MCB - Removal of VCCINT Restrictions to Reach Maximum DDR3 Data Rates


Previously communicated restrictions on VCCINT to reach the maximum Spartan-6 MCB DDR3 data rates have been removed.These restrictions required a tighter VCCINT voltage range as well as a UCF constraint (CONFIG MCB_PERFORMANCE=EXTENDED;) to set the extended mode in software.Spartan-6 MCB DDR3 interfaces can operate at the maximum data rates under the standard VCCINT range as follows:

This change applies to all Spartan-6 production devices shipped (past, present and future), but does not apply to Engineering Sample (ES) devices.

NOTE: The VCCINT restrictions still exist for DDR2.For full details on the DDR2 restrictions, see (Xilinx Answer 35818).


The MIG 3.5-3.7 software included the Extended MCB option on the Memory Selection screen.Selecting the option enabled the extended MCB performance range and set the CONFIG MCB_PERFORMANCE=EXTENDED in the generated UCF.Starting with the MIG 3.8 software(to be released with the ISE 13.2 software), the GUI option will be removed and the generated UCF will always contain the CONFIG MCB_PERFORMANCE = EXTENDED constraint setting. While all production devices are now qualified for operation at the maximum DDR3 data rates over the standardVCCINT range (1.14V to 1.26V), the constraint is still required for the ISE timing tools to properly analyze the interface timing and must not be removed from the UCF file.

Until the MIG 3.8 softwareis available, you can take advantage of the new DDR3 specifications by ensuring that the Extended Performance GUI option is set in the MIG softwareand that the devices operatewithin the standardVCCINT voltage specification.

Linked Answer Records

Master Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
AR# 41520
Date Created 04/12/2011
Last Updated 02/06/2013
Status Active
Type Design Advisory
  • Spartan-6 LX
  • Spartan-6 LXT
  • MIG