AR# 41520 Design Advisory for Spartan-6 MCB - Removal of VCCINT Restrictions to Reach Maximum DDR3 Data Rates
Description
This change applies to all Spartan-6 production devices shipped (past, present and future), but does not apply to Engineering Sample (ES) devices.
NOTE: The VCCINT restrictions still exist for DDR2.For full details on the DDR2 restrictions, see (Xilinx Answer 35818).
Solution
The MIG 3.5-3.7 software included the Extended MCB option on the Memory Selection screen.Selecting the option enabled the extended MCB performance range and set the CONFIG MCB_PERFORMANCE=EXTENDED in the generated UCF.Starting with the MIG 3.8 software(to be released with the ISE 13.2 software), the GUI option will be removed and the generated UCF will always contain the CONFIG MCB_PERFORMANCE = EXTENDED constraint setting. While all production devices are now qualified for operation at the maximum DDR3 data rates over the standardVCCINT range (1.14V to 1.26V), the constraint is still required for the ISE timing tools to properly analyze the interface timing and must not be removed from the UCF file.
Until the MIG 3.8 softwareis available, you can take advantage of the new DDR3 specifications by ensuring that the Extended Performance GUI option is set in the MIG softwareand that the devices operatewithin the standardVCCINT voltage specification.
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33566 | Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores | N/A | N/A |
| 34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |