We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41530

Xilinx Obsolete Device Solution Center - Clocking for devices covered by XCN12026


Note: This Answer Record is part of the Xilinx Obsolete Device Solution Center (Xilinx Answer 40174)whichis available to address questions related to obsolete devices. Specifically, the devices covered by XCN12026.


For general clocking issues, please refer to the Clocking Debug Guide.

(Xilinx Answer 9586)Virtex/Virtex-E DLL reset requirement
(Xilinx Answer 11778)Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures correctly after PROG is pulsed, but DLL/DCM/DCI does not function correctly when reconfigured
(Xilinx Answer 15130)Virtex-II/Virtex-II Pro DCM - To use variable phase shift, a BitGen option must be set and phase shift must be in the positive range
(Xilinx Answer 14425)Virtex-II/-II Pro/-4/-5 FPGA DCM - Resetting after configuration is strongly recommended for a DCM that is configured with external or internal feedback (VHDL/Verilog)
(Xilinx Answer 29845)Spartan-II, Spartan-IIE, Virtex, Virtex-E - CLKDV output of the DLL does not toggle

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
41516 Xilinx Obsolete Device Solution Center - Fabric for devices covered by XCN12026 N/A N/A

Associated Answer Records

AR# 41530
Date Created 04/11/2011
Last Updated 11/27/2012
Status Active
Type General Article
  • Spartan-IIE
  • Spartan-IIE XA
  • Virtex-E
  • More
  • Virtex-E QPro
  • Virtex-EM
  • Virtex-II
  • Less