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AR# 41579

Modelsim Error - Failed to find 'PLL_LOCKG' in hierarchical name

Description

I have been using ISE10.1.03. for simulation.

After upgrading to ISE 13.1, I am receiving the following error in ModelSim.


do tst_pcie_auro.do
# vsim +notimingchecks +TESTNAME=pcie_write_test0 -L work -L secureip -L unisims_ver work.board_top glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# ** Error: d:/Xilinx/13.1/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v(1108): Failed to find 'PLL_LOCKG' in hierarchical name.
# ** Error: d:/Xilinx/13.1/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v(1108): Failed to find 'PLL_LOCKG' in hierarchical name.
# ** Error: d:/Xilinx/13.1/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v(1108): Failed to find 'PLL_LOCKG' in hierarchical name.
# ** Error: d:/Xilinx/13.1/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v(1108): Failed to find 'PLL_LOCKG' in hierarchical name.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./tst_pcie_auro.do PAUSED at line 3

All 13.1 simulation libraries have been successfully compiled with CompXlib.

How can I resolve this?

Solution

This error occurs because the old (10.1.03i) glbl.v was compiled and loaded.

PLL_LOCKG is defined in the 13.1 glbl.v, but not in the old one.

tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

If you are using a simulation DO script generated by Coregen, make sure that your $XILINX environment variable points to the desired version.

NOTE: Starting from 12.1, the installer does not set global environment variables as it previously did.

If $XILINX is referenced as part of the pathname of glbl.v, (for example $env(XILINX)/verilog/src/glbl.v), you will have to either manually modify $XILINX to 13.1 or replace it with the full name in the simulation script.

AR# 41579
Date Created 04/01/2011
Last Updated 01/20/2015
Status Active
Type General Article