For the most recent updates to the IP installation instructions for this
core, please go to:
For system requirements:
This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX
Transceiver Wizard v1.6 solution. For the latest core updates, see the product
2. NEW FEATURES
- ISE 12.2 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
4. RESOLVED ISSUES
- CR 544167, 561501, 563751, 560758
5. KNOWN ISSUES
The following are known issues for v1.6 of this core at time of release:
- The transceiver attributes are not validated on the latest production silicon
- When the RX Buffer is bypassed, the RX delay aligner logic uses the DRP Port. Currently, there is no arbitration logic to enable user accesses for the DRP when RX delay aligner is active. The RX delay aligner logic is enabled for line rates 2.4GHz and above. This logic works for silicon revision 2.0 and above.
- The attribute PMA_RX_CFG should be set to 25'h05CE049 for asynchronous PCIE applications. Currently, the value assigned by the wizard is valid for synchronous PCIE applications.
The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
7. OTHER INFORMATION
- Display Port, Fiber Channel 1G, 2G, 4G, OC48, SATA-I and SATA-II protocol files are not tested for compliance
- For Display Port protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=1, TX/RXPLL_DIVSEL_OUT=1
- For SATA-II protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=2, TX/RXPLL_DIVSEL_OUT=1
- The transceiver attributes of v1.6 version of this core support 2.01 silicon revision
8. CORE RELEASE HISTORY
Date By Version Description
07/23/2010 Xilinx, Inc. x.x ISE 12.2 support
04/19/2010 Xilinx, Inc. x.x ISE 12.1 support
12/02/2009 Xilinx, Inc. x.x ISE 11.4 support
09/16/2009 Xilinx, Inc. x.x ISE 11.3 support
06/24/2009 Xilinx, Inc. x.x ISE 11.2 support
04/24/2009 Xilinx, Inc. x.x Initial release