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AR# 41613

7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List

Description

This answer record lists the known issues and answer records associated with the 7 series FPGAs GTX/GTH Transceivers.

Solution

Usage

 

Wizard

  • (Xilinx Answer 54691) IP Release Notes and Known Issues for 7 Series FPGAs Transceivers Wizard for Vivado 2013.1 and newer versions
  • (Xilinx Answer 63817) 7 Series FPGAs Transceivers Wizard Example Design v3.5 - Use of clocking resources to check for tx|rxoutclk
  • (Xilinx Answer 63110) Design Advisory for 7 Series GTH Transceiver Wizard: DFE incorrectly set to HOLD after adaptation in Vivado 2013.4 to 2014.4   
  • (Xilinx Answer 61875) Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete    
  • (Xilinx Answer 59294) Design Advisory GT wizard - CPLL causes power spike on power up for 7 series GTs  
  • (Xilinx Answer 60356) Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates   
  • (Xilinx Answer 59612) 7 Series GTX - buffer bypass mode: how to correctly set the parameter PCS_RSVD_ATTR   
  • (Xilinx Answer 57592) v7ht.tcl file related Warning message while implementing example design using GTX   
  • (Xilinx Answer 61303) 7 Series Transceiver Wizard 3.3 - VHDL errors with selecting 'TX off'  
  • (Xilinx Answer 60489) Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier: GTH/GTP Production RX reset sequence can get stuck 
  • (Xilinx Answer 61155) 7 Series GTH Wizard v3.2 - GT Wizard generates wrong attributes 
  • (Xilinx Answer 59150) 7 Series FPGA GTX/GTH Transceivers Wizard v3.1 - Tx Buffer Bypass does not complete successfully in auto mode  
  • (Xilinx Answer 58244) Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode  
  • (Xilinx Answer 61161) V3.1 - 7 Series FPGAs Transceivers Wizard - An incorrect GTREFCLK port name may be generated in an example design
  • (Xilinx Answer 61154) v3.1 - 7 Series FPGAs Transceivers Wizard - simulation fails if both LPM mode and Near-end PMA Loopback are selected at the same time
  • (Xilinx Answer 60488) 7 Series FPGA Transceivers Wizard v3.0: GTX/GTH/GTP reset sequence might not complete successfully with the reset FSM's from the wizard  
  • (Xilinx Answer 58608) 7 Series FPGAs Transceivers Wizard Example Design v3.0 - Use of clocking resources to check for tx|rxoutclk   
  • (Xilinx Answer 59184) 7 Series FPGAs GTX/GTH Transceivers Wizard v3.1 - EXAMPLE_SIMULATION not passed to gtwizard_0_tx_startup_fsm.v    
  • (Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode 
  • (Xilinx Answer 56117) 7 Series GTX/GTH/GTP TX buffer bypass port settings mismatch with user guide
  • (Xilinx Answer 55791) Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5
  • (Xilinx Answer 55366) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers: Transceiver Wizard Sets Suboptimal RX Termination Use Modes 
  • (Xilinx Answer 53396) 7 Series FPGAs Transceiver Wizard v2.4 - Known Issues and Release Notes
  • (Xilinx Answer 52868) 7 Series FPGA GTX Transceivers: Line rate/USRCLK limitation for -1 speed grade in 16-bit data path mode
  • (Xilinx Answer 52263) 7 Series FPGAs Transceivers Wizard v2.3 - Known Issues and Release Notes
  • (Xilinx Answer 50299) 7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores - Support for GTX Transceivers in Zynq Devices
  • (Xilinx Answer 50890) 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2/2012.3/2012.4
  • (Xilinx Answer 50827) 7 Series FPGAs Transceivers Wizard v2.2 - Known Issues and Release Notes
  • (Xilinx Answer 47477) 7 Series FPGAs Transceivers Wizard v2.1 - Known Issues and Release Notes
  • (Xilinx Answer 47304) Aurora 8B10B v8.1/64B66B v7.1 and 7 series Transceiver Wizard - How to generate Aurora cores/GT wrappers for XQ7VX690T/TL RF1930 device?
  • (Xilinx Answer 46048) 7 Series FPGAs Transceivers Wizard - What silicon revisions are supported by different Wizard or ISE design tool versions?
  • (Xilinx Answer 47054) 7 Series FPGAs Transceivers Wizard - User defined comma for SONET not allowed
  • (Xilinx Answer 45685) 7 Series FPGAs Transceivers Wizard v1.6 - Known Issues and Release Notes
  • (Xilinx Answer 44988) 7 Series FPGAs Transceivers Wizard v1.5 - Incorrect Internal and External Data Widths with 8B10B
  • (Xilinx Answer 44463) 7 Series FPGAs Transceivers Wizard v1.5 - Known Issues and Release Notes
  • (Xilinx Answer 42809) 7 Series FPGAs Transceivers Wizard v1.4 - Known Issues and Release Notes
  • (Xilinx Answer 40748) 7 Series FPGAs Transceivers Wizard v1.3 - Known Issues and Release Notes
  • (Xilinx Answer 41773) 7 Series GT Wizard - Selecting Independent Line Rates in TX and RX
  • (Xilinx Answer 42591) 7 Series FPGA GTX Transceivers - TX/RX Buffer Bypass Default Attribute Settings
  • (Xilinx Answer 47492) 7 Series FPGA GTH/GTP Buffer Bypass Default Attribute Settings
  • (Xilinx Answer 46841) 7 Series FPGAs Transceivers Wizard - Support for Virtex-7 XC7V2000T Initial ES Devices

Simulation

Silicon Revision Specific

  • (Xilinx Answer 56332) Design Advisory for Virtex-7 GTH - QPLL Attribute Updates for Production Silicon
  • (Xilinx Answer 43244) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
  • (Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon
  • (Xilinx Answer 45410) 7 Series FPGA GTX Transceivers - Initial ES to General ES Silicon GTX Migration
  • (Xilinx Answer 47128) Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon
  • (Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers
  • (Xilinx Answer 51625) Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for General Engineering Sample (ES) Silicon
  • (Xilinx Answer 51884) Design Advisory for Kintex-7/Virtex-7 GTX Production Silicon CDR Attribute Updates
  • (Xilinx Answer 53779) Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon
  • (Xilinx Answer 52040) IBERT - EyeScan not supported with 20 and 40-bit RX internal data width in 7 series GTH (GES Silicon)
  • (Xilinx Answer 56820) 7 Series GTX Transceiver - EyeScan Power Consumption in Production Silicon

 

Software

  • (Xilinx Answer 43339) 7 Series FPGA GTX Transceiver Software Use Model Changes
  • (Xilinx Answer 63076) CRITICAL WARNING: [Timing 38-282] reported when GT reference clock is set to 820MHz for -1/-2 speed grades
  • (Xilinx Answer 63225) 7 Series GTX/GTH - Critical Warning is reported when I attempt to use QPLLOUTREFCLK to drive fabric logic
  • (Xilinx Answer 53920) 7 series GTX - placement failed after switching from Virtex-7 to Kintex-7

Protocol Specific

  • (Xilinx Answer 63869) 7 Series FPGA GTX/GTH/GTP Transceivers - Recommendation on CDR usage for SATA protocol 
  • (Xilinx Answer 53364) 7 Series FPGA GTX/GTH Transceivers - Recommendations and Settings for SATA Gen 1, Gen 2, Gen 3 Optimal Performance
  • (Xilinx Answer 44788) 7 Series FPGA GTH Transceivers -PCI-Express Receiver Detection Time
  • (Xilinx Answer 59035) Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46200 7 Series GTP/GTX/GTH - RXBYTEISALIGNED is not always reliable N/A N/A
45685 7 Series FPGAs Transceiver Wizard v1.6 - Known Issues and Release Notes N/A N/A
45598 7 Series FPGA GTX/GTH Transceivers - Quad usage priority information / RCAL master N/A N/A
44988 7 Series FPGAs Transceivers Wizard v1.5 - Incorrect Internal and External Data Widths with 8B10B N/A N/A
44463 7 Series FPGAs Transceiver Wizard v1.5 - Known Issues and Release Notes N/A N/A
43482 7 Series Transceivers - Reset Requirements Upon Configuration N/A N/A
43260 7 Series GTX/GTH Transceivers - RXSLIDE Feature in PMA/Auto Mode Not Supported with RX Buffer Bypass N/A N/A
42842 7 Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISE 13.1 N/A N/A
42809 7 Series FPGAs Transceiver Wizard v1.4 - Known Issues and Release Notes N/A N/A
40748 7 Series FPGAs Transceiver Wizard v1.3 - Known Issues and Release Notes N/A N/A
41451 7 Series GTX Transceivers - What do you connect the MGTVCCAUX to if QPLL is unused? N/A N/A
47054 7 Series FPGAs Transceiver Wizard - User defined comma for SONET not allowed N/A N/A
46048 7 Series FPGA Transceivers Wizard - Which silicon revisions are supported by the different Wizard or ISE/Vivado tool versions? N/A N/A
43339 7 Series FPGA GTX Transceiver - Software Use Model Changes N/A N/A
43244 Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon N/A N/A
42591 7 Series FPGA GTX Transceivers - TX/RX Buffer Bypass Default Attribute Settings N/A N/A
41773 7 Series GT Wizard: Selecting Independent Line Rates in TX and RX N/A N/A
47817 Design Advisory for the Kintex-7 and Virtex-7 GTX Transceiver Power-up/Power-down N/A N/A
50617 Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers N/A N/A
50827 7 Series FPGAs Transceiver Wizard v2.2 - Known Issues and Release Notes N/A N/A
50890 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2/2012.3/2012.4 N/A N/A
50299 7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores - Support for GTX Transceivers in Zynq Devices N/A N/A
44549 7 Series FPGA GTX/GTH/GTP Transceivers - Reference clock phase noise masks N/A N/A
52744 Virtex-7 FPGA GTH Transceivers - Power Supply Grouping Per Package N/A N/A
52668 Virtex-7 FPGA GTX/GTH Transceivers - Multi-lane buffer bypass not supported across SLR boundary N/A N/A
52868 7 Series FPGA GTX Transceivers - Line rate/USRCLK limitation for -1 speed grade in 16-bit data path mode N/A N/A
51198 7 Series GTX Fast Simulation Models - Speed up of GTXE components for the ISE environment N/A N/A
55791 Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5 N/A N/A
54691 7 Series FPGAs Transceivers Wizard - Release Notes and Known Issues for Vivado 2013.1 and newer versions N/A N/A
AR# 41613
Date Created 04/18/2011
Last Updated 05/18/2015
Status Active
Type Known Issues
Devices
  • Virtex-7
  • Artix-7
  • Kintex-7
  • Virtex-7 HT
IP
  • 7 Series FPGAs Transceivers Wizard