Usage

• (Xilinx Answer 51825) Usage of CTLE Auto Adapting Mode in 7 series FPGAs GTX
• (Xilinx Answer 52431) Virtex-7 FPGA GTH Transceivers - ACJTAG Use Mode in Engineering Sample (ES) Silicon
• (Xilinx Answer 52844) 7 Series GTX GTH Production Silicon - Correct setup when OOB is not used
• (Xilinx Answer 45148) 7 Series GTX/GTH CTLE and DFE frozen setup
• (Xilinx Answer 46024) 7 Series GTX - How do you override the Phase Interpolator (PI) phase?
• (Xilinx Answer 52744) Virtex-7 FPGA GTH Transceivers: Power Supply Grouping Per Package
• (Xilinx Answer 52668) Virtex-7 FPGA GTX/GTH Transceivers: Multi-lane buffer bypass not supported across SLR boundary
• (Xilinx Answer 44549) 7 Series FPGA GTX/GTH/GTP Transceivers - Reference clock phase noise masks
• (Xilinx Answer 44587) 7 Series GTX/GTH/GTP Transceivers: RX OOB use modes
• (Xilinx Answer 47443) Design Advisory for 7 Series FPGAs GTH Transceiver Power-Up/Power-Down
• (Xilinx Answer 47817) Design Advisory for the Kintex-7 and Virtex-7 GTX Transceiver Power-Up/Power-Down
• (Xilinx Answer 47342) Design Advisory for Virtex-7 GTH Serial Transceiver Package Diagram corrections
• (Xilinx Answer 47307) 7 Series FPGA Transceivers - How to connect the receiver pins MGTRXP/N when RX not used?
• (Xilinx Answer 47328) 7 Series GTX-Loopback mode known limitations
• (Xilinx Answer 41451) 7 Series GTX Transceivers -What to connect the MGTVCCAUX to if QPLL is unused?
• (Xilinx Answer 43260) 7 Series GTX Transceivers -RXSLIDE feature in PMA mode not supported with RX buffer bypass
• (Xilinx Answer 43482) 7 Series GTX Transceivers -Reset requirements upon configuration
• (Xilinx Answer 43420) Xilinx Serial Transceivers - Can the LVDS standard be used for reference clocks?
• (Xilinx Answer 45598) 7 Series FPGA GTX/GTH Transceivers -Quad Usage Priority Information
• (Xilinx Answer 46200) 7 Series GTP/GTX/GTH RXBYTEISALIGNED is not always reliable
• (Xilinx Answer 47331) 7 Series FPGA GTX/GTH Transceivers - No Power Sequencing Requirement for MGTAVTT/MGTVCCAUX

Wizard

• (Xilinx Answer 53396) 7 Series FPGAs Transceiver Wizard v2.4 - Known Issues and Release Notes
• (Xilinx Answer 52868) 7 Series FPGA GTX Transceivers: Line rate/USRCLK limitation for -1 speed grade in 16-bit data path mode
• (Xilinx Answer 52263) 7 Series FPGAs Transceivers Wizard v2.3 - Known Issues and Release Notes
• (Xilinx Answer 50299) 7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores - Support for GTX Transceivers in Zynq Devices
• (Xilinx Answer 50890) 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2/2012.3/2012.4
• (Xilinx Answer 50827) 7 Series FPGAs Transceivers Wizard v2.2 - Known Issues and Release Notes
• (Xilinx Answer 47477) 7 Series FPGAs Transceivers Wizard v2.1 - Known Issues and Release Notes
• (Xilinx Answer 47304) Aurora 8B10B v8.1/64B66B v7.1 and 7-series Transceiver Wizard - How to generate Aurora cores/GT wrappers for XQ7VX690T/TL RF1930 device?
• (Xilinx Answer 46048) 7 Series FPGAs Transceivers Wizard - What silicon revisions are supported by different Wizard or ISE design tool versions?
• (Xilinx Answer 47054) 7 Series FPGAs Transceivers Wizard - User defined comma for SONET not allowed
• (Xilinx Answer 45685) 7 Series FPGAs Transceivers Wizard v1.6 - Known Issues and Release Notes
• (Xilinx Answer 44988) 7 Series FPGAs Transceivers Wizard v1.5 - Incorrect Internal and External Data Widths with 8B10B
• (Xilinx Answer 44463) 7 Series FPGAs Transceivers Wizard v1.5 - Known Issues and Release Notes
• (Xilinx Answer 42809) 7 Series FPGAs Transceivers Wizard v1.4 - Known Issues and Release Notes
• (Xilinx Answer 40748) 7 Series FPGAs Transceivers Wizard v1.3 - Known Issues and Release Notes
• (Xilinx Answer 41773) 7 Series GT Wizard - Selecting Independent Line Rates in TX and RX
• (Xilinx Answer 42591) 7 Series FPGA GTX Transceivers - TX/RX Buffer Bypass Default Attribute Settings
• (Xilinx Answer 47492) 7 Series FPGA GTH/GTP Buffer Bypass Default Attribute Settings
• (Xilinx Answer 46841) 7 Series FPGAs Transceivers Wizard - Support for Virtex-7 XC7V2000T Initial ES Devices 

Simulation

• (Xilinx Answer 42842) 7 Series GTX Transceiver PLLREFCLK selection change causing simulation issue in ISE Design Suite 13.1
• (Xilinx Answer 47318) 7 Series FPGA GTH Transceivers - Long simulation run times
• (Xilinx Answer 47494) 7 Series GTX IBIS - AMI Model Advanced Use Mode
• (Xilinx Answer 51198) 7 Series GTX Fast Simulation Models - Speed up of GTXE components for the ISE environment

• (Xilinx Answer 47171) Modelsim 10.1 problems with Serial Transceivers

Silicon Revision Specific

• (Xilinx Answer 43244) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
• (Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon
• (Xilinx Answer 45410) 7 Series FPGA GTX Transceivers - Initial ES to General ES Silicon GTX Migration
• (Xilinx Answer 47128) Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon
• (Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers
• (Xilinx Answer 51625) Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for General Engineering Sample (ES) Silicon
• (Xilinx Answer 51884) Design Advisory for Kintex-7/Virtex-7 GTX Production Silicon CDR Attribute Updates
• (Xilinx Answer 53779) Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon
• (Xilinx Answer 52040) IBERT - EyeScan not supported with 20 and 40-bit RX internal datawidth in 7 series GTH (GES Silicon)
  

Software

• (Xilinx Answer 43339) 7 Series FPGA GTX Transceiver Software Use Model Changes

Protocol Specific

• (Xilinx Answer 53364) 7 Series FPGA GTX/GTH Transceivers - Recommendations and Settings for SATA Gen 1, Gen 2, Gen 3 Optimal Performance
• (Xilinx Answer 44788) 7 Series FPGA GTH Transceivers -PCI-Express Receiver Detection Time