We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41652

MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator error_status does not latch correct data


The error_status output signal coming out of tg_status.vhd/v file does notlatch the error data due to different number of pipeline stages on the various parts of the data in the read_data_path.vhd/v module.

Neither the expected or actual data values at the time of the error status transistion will align, so the error_status can not actually be used to view the error values for either the expected or the actual data.

The expected data captured by tg_status of the value cmp_data_o does not align with data_error_o and appears to be off by one cycle while theactual data captured by tg_status of the value rd_mdata_o does not align with data_error_o and appears to be off by two clock cycles.


read_data_path.vhd/.v must be modified to account for the extra pipeline stages. The following read_data_path.vhd/.v contain the added pipeline stages and can replace the existing read_data_path.vhd/.v.

This will be fixed in the 13.3 release.

Linked Answer Records

Associated Answer Records

AR# 41652
Date 05/19/2012
Status Archive
Type Known Issues
  • Virtex-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LX
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • MIG
Page Bookmarked