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AR# 41653

MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd

Description

Masking of address data is not consistent in the cmd_gen.vhd module, which can result in two different addresses being used in the remainder of the code for the Virtex-6 FPGA BL8 case.Due to the different instantiation of the data generator in the read/write paths, this leads to false compare errors.

The fixed address comes from the MIG init_mem_pattern_ctr.vhd module:

fixed_addr_o <= "00000000000000000001001000110100";

This flows into the cmd_gen.vhd module and turns into addr_out, which then becomes masked in two different places:

ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN

IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO4) & "0000") ;
END IF;

ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) &"0000") ;

Note that the pipe_data_in is masking off five LSBs for BL8, but the m_addr_o is only masking off four LSBs regardless of burst length, and that the fixed address specified by default has a '1' bit at bit 4. So this means that the resulting values are going to be different.

Solution

Because of the above code statements, a situation can occur where the write generator is seeded with one value and the read generator is seeded with another, because the fixed address was masked differently up stream.Therefore, thecomparison fails.

As a workaround, you can change the fixed address in the init_mem_pattern_ctr.vhd module so that it ends up aligned regardless of the two different masks being applied by the rest of the code:

fixed_addr_o <= "00000000000000000001001000110100";

fixed_addr_o <= "00000000000000000001001000100100";

Theother tests work fine because they are going to generate BL8-aligned addresses. This is scheduled to be fixed in the ISE 13.3 software release.

Linked Answer Records

Associated Answer Records

AR# 41653
Date Created 06/08/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LX
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
IP
  • MIG