The Configuration Register 2 contains two power down bits, PD0 and PD1, that can be used to either power down ADC B or the XADC block.
Setting PD1=PD=1 powers down the XADC.
Note: In Virtex-6 FPGAs, the System Monitor was powered down by grounding the AVdd; however, in the 7 Series XADC the Vccadc should never be tied to GND.
Even if the XADC is not used it should be connected to VCCAUX.
The XADC User Guide gives details on what each port should be connected to if the XADC is not used in the Package Pins section.