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AR# 41699

7 Series XADC - How do you power down the XADC?


In the 7 Series FPGAs, how do you power down the XADC?


The Configuration Register 2 contains two power down bits, PD0 and PD1, that can be used to either power down ADC B or the XADC block.

Setting PD1=PD=1 powers down the XADC.

NOTE : In Virtex-6 FPGA the System Monitor was powered down by grounding the AVdd; however, in the 7-Series XADC the Vccadc should never be tied to GND.
AR# 41699
Date Created 05/02/2011
Last Updated 10/12/2011
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT