No, FPGA banks cannot be shared between multiple memory controllers.
DDR3 SDRAM Bank Sharing
For DDR3 SDRAM, each interface requires a unique PHY Control Block in all interface banks. The PHY Control Block is dedicated logic that controls the FIFOs and Phasers within the bank. Both Address/Control and Data Byte Groups use the PHY Control Block within the bank and only one PHY Control Block exists in an FPGA bank. Therefore, it is not possible to share a bank between two DDR3 SDRAM interfaces. This is documented in the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
http://www.xilinx.com/support/documentation/ip_documentation/ug586_7Series_MIS.pdf
QDRII+/RLDRAMII Bank Sharing
While QDRII+/RLDRAMII only use the PHY Control Block on the outbound (write) path, Xilinx currently only supports unique FPGA banks for all memory interfaces in 7 series. If this were supported, it would have to be for interfaces operating at the same frequency. Xilinx is currently determining the feasibility of a bank sharing solution. If it is found to be feasible, a schedule for development would need to be set. Until this is complete, anything outside of a unique bank placement for each controller cannot be recommended.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51317 | Xilinx MIG Solution Center, MIG 7 Series Design Assistant - Verify pin-out/banking requirements are met | N/A | N/A |
| 51676 | MIG 7 Series Solution DDR2/DDR3 - Supported Features | N/A | N/A |