UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41720

13.1 PlanAhead - HDL Design Errors when Importing a MIG Design

Description

When I import an RTL design generated from MIG, I encounter the following errors:

"Designutils-73 Failed to Elaborate HDL Design"

"ERROR: [HDL-1401] Signal raw_not_ecc[3] in unit ui_wr_data(100,32,4,"OFF","OFF",5)(1,3,1,3) is connected to following multiple drivers: [C:\My_designs\project_1\project_1.srcs\sources_1\imports\rtl\ui\ui_wr_data.vhd:567]
ERROR: [HDL-1379] Driver 0: output signal raw_not_ecc[3] of instance Ground [C:\My_designs\project_1\project_1.srcs\sources_1\imports\rtl\ui\ui_wr_data.vhd:582]
ERROR: [HDL-1379] Driver 1: output signal raw_not_ecc[3] of instance Buffer [C:\My_designs\project_1\project_1.srcs\sources_1\imports\rtl\ui\ui_wr_data.vhd:567]"

Solution

This issue only occurs in Windows OS. Linux OS is not affected. This issue is fixed in the v13.2 PlanAhead tool.
To work around this issue, run Synthesize in the ISE software, and then run the PlanAhead tool based on the netlist entry.
AR# 41720
Date Created 07/14/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Tools
  • PlanAhead - 13.1
IP
  • MIG