I see the following warning in the XST report:
However, when I open the design in Technology Schematic or in FPGA Editor I see that the port is connected in the design.
Is this a known issue?
There is a known issue with XST incorrectly highlighting this warning.
This issue is fixed in ISE 14.1.
In the future, as a good practice to determine if these XST warnings are valid or not, you can check the MAP report.
If the input is not being used, the MAP report should report that the input has no load and a corresponding message should appear in Section 3.