There have been instances where the PlanAhead toolmodifies the clock dedicated route constraints in the ".ucf" file.The same design and constraint file runs without error in Project Navigator. For example, following is what the constraint in the original ".ucf" file looks like:
PIN "clock/BUFGCE_td/BUFGMUX.O" CLOCK_DEDICATED_ROUTE = FALSE;
The ".ucf" file in the run directory (impl_1_1) looks like the following:
PIN "clock/BUFGCE_td.O" CLOCK_DEDICATED_ROUTE = FALSE;
Notice that theBUFGMUX.O is missing.
This leads to the following error message:
"ERROR:Place:1205 - This design contains a global buffer instance, <clock/BUFGCE_td/BUFGMUX>, driving the net, <my_clk>, that is driving the following (first 30) non-clock load pins off chip....< PIN "clock/BUFGCE_td/BUFGMUX.O" CLOCK_DEDICATED_ROUTE = FALSE; >"
In the example shown,BUFGMUX.O is an internal cell name and does not exist in the design netlist. The PlanAhead toolonly recognizes a limited number of internal cell names.It is recommended that actualnetlist/design names be used in the constraint file(s).The place and route software does not fail because the internal names are expanded before this check is done.
To work around the issue, you must manually modify the ".ucf" file in the impl directory, or modify the original constraint file so that it does not use internal cell names.
This issue is resolved in the PlanAhead 13.3 tool.