For any protocol or core that requires access to the management interface from the top module, you will find that this is not possible in v1.7 of the Virtex-6 FPGA Transceivers Wizard as it has been disconnected internally to be used for reset purposes.
An example is the 10G BASE-R core example design thatincludes an arbiter on the managementinterface to allow up to 4 GTH Transceiversto be controlled through the single interface on the GTH and, hence, it needs to use this management interface.
Fix and Work-around
This issue is fixed by adding a multiplexer to select between the management interface and the reset module interface, and switchingthe control to the management interface once the resetis completed. This fix is available inv1.8 of the Virtex-6 GTH Transceivers Wizardreleased with ISE 13.2 tools.
The following steps can be followed as a workaround when usingwizard versions earlier than v1.8.
In the GTH_RESET block, add an output port 'mgmt_hold_out' which is set to '1' while the reset FSM is not 'DONE', and then set it to '0' when mgmt_op_done is set to '1'. The output is then used in the QUAD block to select between the MGMT* inputs to the QUAD block and the GTH_RESET mgmt* outputs.Note that the disable_drp_gt signal is created to allow both the GTH_RESET and my external blocks to access the management interface.
disable_drp_gt <= disable_drp_i or DISABLEDRP_IN;
lane_sel_proc : process (mgmt_hold_out_i, MGMTPCSLANESEL_IN, mgmtpcslanesel_i, MGMTPCSREGRD_IN, MGMTPCSREGWR_IN, MGMTPCSMMDADDR_IN, MGMTPCSREGADDR_IN, MGMTPCSWRDATA_IN, mgmtpcsregrd_i, mgmtpcsregwr_i, mgmtpcsmmdaddr_i, mgmtpcsregaddr_i, mgmtpcswrdata_i)
if(mgmt_hold_out_i = '0') then
lane_sel <= MGMTPCSLANESEL_IN;
mgmt_rd <= MGMTPCSREGRD_IN;
mgmt_wr <= MGMTPCSREGWR_IN;
mgmt_addr <= MGMTPCSMMDADDR_IN & MGMTPCSREGADDR_IN;
mgmt_wrdata <= MGMTPCSWRDATA_IN;
lane_sel <= mgmtpcslanesel_i;
mgmt_rd <= mgmtpcsregrd_i;
mgmt_wr <= mgmtpcsregwr_i;
mgmt_addr <= mgmtpcsmmdaddr_i & mgmtpcsregaddr_i;
mgmt_wrdata <= mgmtpcswrdata_i;
MGMTPCSRDACK_OUT <= mgmtpcsrdack_i;
MGMTPCSRDDATA_OUT <= mgmtpcsrddata_i;