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AR# 41780

Virtex-6 - Bitgen DRC bram warning incorrect


I am inferring a BRAM with independent read and write clock.

When I run bitgen I get the following warning:

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM
instance, Mram_mem_data, are using the same clock signal(synchronous
clocking) with WRITE_FIRST mode specified. This configuration may encounter
address collisions if the same address appears on both ports. It is suggested
for this configuration to use READ_FIRST mode to avoid any conditions for
address collision. See the Virtex-6 FPGA Memory Resources User Guide for
additional information.

Does bitgen or MAP/PAR modify the design and uses the same clock? In the RTL design the BRAM are clocked with the independent clocks iclock and oclock.


This is an incorrect message and can be ignored. This issue has been fixed in ISE 13.2 software.
AR# 41780
Date Created 07/15/2011
Last Updated 07/18/2011
Status Active
Type General Article