The purpose of the Thevenintermination was to protect the CCLK pin from ringing. Previous FPGA design was more susceptible to it (ringing would result in double clocking) and it was fixed in the7 series. The issue was that the internal CCLK would drive out to the pin, which had its input buffer enabled, so it would read the CCLK transitions on the pin. If there was reflection, then the CCLK input buffer could read that as another clock edge and cause data corruption. In the 7 series, the CCLK input buffer is not used; the CCLK is branched off internally before it goes out to the pin. Hence,it is less susceptible to issues with double clocking.