We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41782

7 Series and UltraScale - Why is there no longer a recommendation for Thevenin termination on the CCLK pin for configuration?


Why do 7 series and UltraScale FPGAs not use external Thevenin termination?

Is there any difference between the CCLK Clock Buffer in 7 series/UltraScale FPGAs and Virtex-5/-6 FPGAs?


The purpose of the Thevenin termination was to protect the CCLK pin from ringing. Previous FPGA design was more susceptible to it (ringing would result in double clocking) but it was fixed in the 7 series and UltraScale devices.

The issue was that the internal CCLK would drive out to the pin, which had its input buffer enabled, so it would read the CCLK transitions on the pin. If there was reflection, then the CCLK input buffer could read that as another clock edge and cause data corruption.

In the 7 series and UltraScale devices, the CCLK input buffer is not used. The CCLK is branched off internally before it goes out to the pin.

As a result, it is less susceptible to issues with double clocking.

AR# 41782
Date Created 04/14/2011
Last Updated 01/12/2016
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
  • More
  • Artix-7
  • Kintex UltraScale
  • Virtex UltraScale
  • Less