When implementing a design in MIG 3.7 that uses the Suspend feature, a glitch can be generated when exiting suspend mode on pins that are fed by the OSERDES2.
What is the cause of the glitch and how can it be avoided?
Version Fixed: ISE13.2 (v3.8)
When the Spartan-6 FPGA is placed into Suspend, the PLL and the BUFPLL_MCB lose lock. When exiting from suspend and while acquiring lock, the outputs of the BUFPLL_MCB pll_ce_0 and sysclk_2x might not have a defined relationship.
Therefore, it is possible for the pll_ce_0 signal to inadvertently assert the select input of the cascade in the MUX of the OSERDES2 and the sysclk_2x signal to clock in the contents of the D4 and D3 Flip-Flops.
Because those registers are not used when the OSERDES2 is used in DDR mode, they contain '0'. This can result in a low glitch on the ouput of the OSERDES2.
To avoid this, the .OCE port of the OSERDES2 should only be enabled after the BUFPLL_MCB LOCK signal is asserted. This will be automatically implemented starting in MIG 3.8.