MIG v3.7 Spartan-6 MCB - Certain User Port Configurations do not work for VHDL designs

AR#	41822	Search For Another Answer
Topic	MIG
Last Updated	04/22/2011
Status	Active

Description

When implementing a Spartan-6 MCB design in MIG 3.7 in VHDL, for certain port configurations some user ports do not get enabled.  Any data that gets written to the disabled ports is dropped by the MCB and no data appears on the ports during reads. This issue does not exist in earlier version of MIG.  This issue affects only VHDL based MIG 3.7 MCB designs for Spartan-6 FPGA; Verilog based designs are not affected.  The issue will be fixed in MIG 3.8.

Solution

This issue only affects MCB VHDL designs that are generated in MIG 3.7.  The issue is that the Cx_ARB_TIME_SLOT_? constants in example_top.vhd or the top-level user design are assigned the logical port values instead of the physical port values.  This means that for certain port configurations the user has to change the Cx_ARB_TIME_SLOT_? values in example_top.vhd or the top-level user design from the logical port values to the physical port values.  The port configurations that are affected are the ones where the physical port numbers are different than the logical port numbers.  See the table below for the logical and physical port numbers for all possible user port configurations.  For more information on Port Configurations of the MCB see the "MCB Functional Description" -> "Port Configurations" section of the Spartan-6 FPGA Memory Controller User Guide (UG388). 

Port Configuration	Logical Ports	Physical Ports
2 32-bit unidirectional & 4-32-bit bidirectional	012345	012345
4 32-bit bidirectional ports	0123	0124
1 64-bit & 2 - 32-bit bidirectional	012	024
2 64-bit bidirectional	01	02
1 128-bit bidirectional	0	0

 

Example

For a 2 64-bit bidirectional port configuration with a round-robin arbitration scheme for MCB3 MIG 3.7 would incorrectly assign the following  Cx_ARB_TIME_SLOT_? constants:

   constant C3_ARB_TIME_SLOT_0      : bit_vector(5 downto 0) := o"01";
   constant C3_ARB_TIME_SLOT_1      : bit_vector(5 downto 0) := o"10";
   constant C3_ARB_TIME_SLOT_2      : bit_vector(5 downto 0) := o"01";
   constant C3_ARB_TIME_SLOT_3      : bit_vector(5 downto 0) := o"10";
   constant C3_ARB_TIME_SLOT_4      : bit_vector(5 downto 0) := o"01";
   constant C3_ARB_TIME_SLOT_5      : bit_vector(5 downto 0) := o"10";
   constant C3_ARB_TIME_SLOT_6      : bit_vector(5 downto 0) := o"01";
   constant C3_ARB_TIME_SLOT_7      : bit_vector(5 downto 0) := o"10";
   constant C3_ARB_TIME_SLOT_8      : bit_vector(5 downto 0) := o"01";
   constant C3_ARB_TIME_SLOT_9      : bit_vector(5 downto 0) := o"10";
   constant C3_ARB_TIME_SLOT_10     : bit_vector(5 downto 0) := o"01";
   constant C3_ARB_TIME_SLOT_11     : bit_vector(5 downto 0) := o"10";

To make the arbitration scheme work the user would have to change the values of the constants as follows:

   constant C3_ARB_TIME_SLOT_0      : bit_vector(5 downto 0) := o"02";
   constant C3_ARB_TIME_SLOT_1      : bit_vector(5 downto 0) := o"20";
   constant C3_ARB_TIME_SLOT_2      : bit_vector(5 downto 0) := o"02";
   constant C3_ARB_TIME_SLOT_3      : bit_vector(5 downto 0) := o"20";
   constant C3_ARB_TIME_SLOT_4      : bit_vector(5 downto 0) := o"02";
   constant C3_ARB_TIME_SLOT_5      : bit_vector(5 downto 0) := o"20";
   constant C3_ARB_TIME_SLOT_6      : bit_vector(5 downto 0) := o"02";
   constant C3_ARB_TIME_SLOT_7      : bit_vector(5 downto 0) := o"20";
   constant C3_ARB_TIME_SLOT_8      : bit_vector(5 downto 0) := o"02";
   constant C3_ARB_TIME_SLOT_9      : bit_vector(5 downto 0) := o"20";
   constant C3_ARB_TIME_SLOT_10     : bit_vector(5 downto 0) := o"02";
   constant C3_ARB_TIME_SLOT_11     : bit_vector(5 downto 0) := o"20";