UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41876

13.1 - "FATAL_ERROR:Pack:pksbarouter.c:1967" when using DDR2 S and R Pins

Description

The following error occurs during the packing phase of the map command:
"FATAL_ERROR:Pack:pksbarouter.c:1967:1.15 - An attempt was made to connect signals rst_100 and vid_in<1> to the same load pin. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."

What does it mean and what can be done to avoid it?

Solution

This error involves the S and R inputs of the IDDR2 and ODDR2 components. According to page 54 of the Spartan-6 FPGA SelectIO Resources User Guide (UG381), "Software will issue an error if both R and S are connected":
http://www.xilinx.com/support/documentation/user_guides/ug381.pdf.

In this case, both were connected. Disconnecting the S pin overcomes the issue and the design then completes implementation.

The error handling is scheduled to be improved in ISE Design Suite13.3 so that a user error is printed rather than this cryptic fatal error.

Linked Answer Records

Associated Answer Records

AR# 41876
Date Created 08/17/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q