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AR# 4190

FPGA Configuration - State of Dout pin before configuration in 4000 series devices


Users can delay configuration by holding the INIT pin low. This causes the I/O of the device to be placed in a tristate condition (with the exception of Dout).


When the user holds PROG or INIT low before configuration, Dout will be driving a "1". The "1" will be driven until configuration begins at which time the 40 bit header will be passed or the device starts to pass on data in a daisy chain. For more information on configuration, please see the data book.


Associated Attachments

Name File Size File Type
ar54190.zip 5 KB ZIP
AR# 4190
Date Created 08/21/2007
Last Updated 05/26/2014
Status Archive
Type Known Issues