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AR# 41923

MIG v3.61 Virtex-5 DDR2 - MT47H512M8 generates incorrect COL_WIDTH

Description

When I look at the HDL in my MIG design, I see that the COL_WIDTH parameter is set to 11 when it should be set to a value of 10.

parameter COL_WIDTH = 11, // # of memory column bits.

Solution

To work around the problem, set the top-level parameter "COL_WIDTH" to a value of 10. This should be set in sim_tb_top.v/vhd for simulation and <design_name>.v/vhd for implementation and hardware.

If this is a multi-controller design, then the parameter will be called C#_DDR2_COL_WIDTH.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 41923
Date Created 04/27/2011
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-5 LXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
Tools
  • ISE Design Suite - 13.1
IP
  • MIG