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AR# 41924

ChipScope IBERT - Configuring IBERT with Serial/SelectMAP configuration mode results in device not starting up

Description


I am using an external MCU to control the bit/config image downloading process. All other bit files can be successfully downloaded into FPGA part, but the ibert.bit always fails with the following status register value:

'1': Reading status register contents...
[0] CRC ERROR : 0
[1] DECRYPTOR ERROR : 0
[2] PLL LOCK STATUS : 1
[3] DCI MATCH STATUS : 1
[4] END OF STARTUP (EOS) STATUS : 0
[5] GTS_CFG_B STATUS : 0
[6] GWE STATUS : 0
[7] GHIGH STATUS : 1
[8] MODE PIN M[0] : 1
[9] MODE PIN M[1] : 1
[10] MODE PIN M[2] : 1
[11] INIT_B INTERNAL SIGNAL STATUS : 1
[12] INIT_B PIN : 1
[13] DONE INTERNAL SIGNAL STATUS : 0
[14] DONE PIN : 0
[15] IDCODE ERROR : 0
[16] SECURITY ERROR : 0
[17] SYSTEM MONITOR OVER-TEMP ALARM STATUS : 0
[18] CFG STARTUP STATE MACHINE PHASE : 0
[19] CFG STARTUP STATE MACHINE PHASE : 0
[20] CFG STARTUP STATE MACHINE PHASE : 0
[21] RESERVED : 0
[22] SPI FLASH SELECT PIN FS[0] : 1
[23] SPI FLASH SELECT PIN FS[1] : 1
[24] SPI FLASH SELECT PIN FS[2] : 0
[25] CFG BUS WIDTH DETECTION : 0
[26] CFG BUS WIDTH DETECTION : 0
[27] RESERVED : 0
[28] HSWAPEN PIN : 0
[29] BAD PACKET ERROR : 0
[30] RESERVED : 0
[31] EFUSE BUSY STATUS : 0



If I download ibert.bit through the JTAG ports, all is going well.

Solution

By default IBERT Core Generator assumes you download ibert.bit through the JTAG ports as this bit is often used only in debug process, so the tool sets the Startup clock to JTAG clock. In serial/SelectMAP configuration mode, after all the data has been properly sent into FPGA, the part will hang in the Startup phase as no JTAG clock is provided.

To solve this issue, we need to modify the Startup clock to CCLK and recalculate the CRC value. (Xilinx Answer 29756) provides a method to automatically generate a ibert.bit with Startup clock changing to CCLK and recalculated CRC value:

1. Invoke iMPACT and ensure Automatic Correction for Startup Clock is selected in Preferences window.
2. Click on Prepare a PROM File to invoke the PROM File Formatter and when you assign the ibert.bit file to generate a PROM file, a warning will come up:

WARNING:iMPACT:2257 - Startup Clock has been changed to 'Cclk' in the bitstream stored in memory, but the original bitstream file remains unchanged. Dumping bit file //ibert_cclktemp.bit...

3. You will see a new .bit file named ibert_cclktemp.bit placed in the original ibert.bit project folder. The bit can be downloaded with serial/SelectMAP configuration methods.
AR# 41924
Date Created 04/25/2011
Last Updated 07/15/2011
Status Active
Type General Article
Devices
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Tools
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