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AR# 41955

Soft Error Mitigation Controller - How is the IP affected by the Spartan-6 9K block RAM issue?


Do the issues concerning the Spartan-6 9K (RAMB8BWER)affect the Spartan-6 Soft Error Mitigation Controller?

Can the user include Spartan-6 9K block RAM in their portion of the design when using the SEM controller?

For more information on the Spartan-6 block RAM concerns, see (Xilinx Answer 39999) and the Spartan-6 Errata (EN148).


When targeting small Spartan-6 devices, the SEM controller can use a 9K (RAMB8BWER) in the design. However, this 9K block RAM does not require initialization, and is not impacted by the 9K block RAM initialization concern discussed in the errata. The SEM controller uses 18K (RAMB16BWER) in all cases where block RAM initialization is needed. For these reasons, the 9K block RAM initialization concern discussed in the errata and (Xilinx Answer 39999) does not impact the SEM core.

The Spartan-6 SEM controller performs configuration readback through the ICAP. However, the SEM controller only reads back type 0 frames. Since only type 0 frames are read back, it does not impact the contents of the 9K block RAM. This means that if the user has 9K block RAM inthe design,it is not subject to the "Configuration Readback When Using 9K Block RAM" item discussed in the errata.

Initial Release
07/06/2011 - Initial Release

AR# 41955
Date Created 06/03/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Spartan-6Q
  • Spartan-6 LX
  • Soft Error Mitigation