MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Cntrl Pins Should be Limited to a Single Bank

AR#	41981	Search For Another Answer
Topic	MIG
Last Updated	08/04/2011
Status	Active

Description

By default, the MIG software places all Address and Control signals into the same bank. However, MIG 7 Series v1.1 and earlier versions do not restrict users from placing Address and Control signals across multiple vertical banks of the same column. To minimize clock skew, Xilinx requires that all Address and Control signals be placed in the same bank.

Solution

For designs that require three banks, the Address and Control signals need to be placed in the center bank. The skew is too large to compensate for designs that require three banks if the PLL in the Address and Control bank is two banks away from the furthest Data bank. This is not a requirement for designs that only require one or two banks.

Future versions of the MIG software, beginning with the ISE 13.3 software and MIG 7 Series v1.3 release, will enforce this requirement during Pin/Bank Selection. This requirement is to be included in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586) starting with the ISE 13.3 software release.