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AR# 41981 MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Cntrl Pins Should be Limited to a Single Bank

Description

By default, the MIG softwareplaces all Address and Control signals into the same bank. However, MIG 7 Series v1.1 and earlier versions do not restrict users from placing Address and Control signals across multiple vertical banks of the same column. To minimize clock skew, Xilinx requires that all Address and Control signals be placed in the same bank.

Solution

For designs that requirethree banks, the Address and Control signals need to be placed in the center bank. The skew is too large to compensate for designs that requirethree banks if the PLL in the Address and Control bank istwo banks away from the furthest Data bank. This is not a requirement for designs that only requireone ortwo banks.

Future versions of the MIG software, beginning with the ISE13.3 software and MIG 7 Series v1.3 release, will enforce this requirement during Pin/Bank Selection. This requirement is to be included in the7 Series FPGAs Memory Interface Solutions User Guide (UG586) starting with the ISE 13.3 software release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43481 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules N/A N/A
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
37498 MIG Design Assistant - Spartan-6 Core Functionality N/A N/A
42024 MIG 7 Series DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM? N/A N/A
34263 Xilinx MIG Solution Center - Documentation N/A N/A
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A

Actions

AR# 41981
Date Created 04/28/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-7
  • Kintex-7
Tools
  • ISE Design Suite - 13.1
IP
  • MIG
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