UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42000

13.1 EDK, ChipScope - "ERROR:PhysDesignRules:2110 - For TDP or SDP mode, REGCLKARDRCLKU should be tied off to 0 when DOA_REG is 0."

Description

When adding any ChipScope core to a design, the following error occurs during BitGen:

ERROR:PhysDesignRules:2110 - Issue with pin connections and/or configuration on block:<Mram_iRAM1>:<RAMB36E1_RAMB36E1>. For TDP or SDP mode, REGCLKARDRCLKU should be tied off to 0 when DOA_REG is 0.

How do I resolve this issue?

Solution

This error is caused by KEEP constraints that are added to ChipScope input signals to make them easier to see in a netlist, or to change in FPGA Editor.

This error can be resolved by disabling the generation of the KEEP constraints by setting the XCO parameter disable_save_keep to true, and regenerating the ChipScope core.
AR# 42000
Date Created 05/31/2011
Last Updated 12/03/2014
Status Active
Type General Article
Tools
  • ChipScope Pro - 13.1
  • EDK - 13.1
IP
  • ChipScope AXI Monitor
  • ChipScope ILA