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AR# 42024 MIG 7 Series DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM?

Description

Does Xilinx specify the recommended trace impedance between the FPGA and the DDR3 SDRAM for the MIG 7 Series DDR3 design?

NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Xilinx recommends 40 ohm traces for DDR3 SDRAM memory interfaces running above 1333 Mb/s. 50 ohm traces can be used for slower data rates. The 7 Series FPGAs Memory Interface Solutions User Guide (UG586) now documents these recommended trace impedances. Please refer to the user guide for additional information.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
46132 MIG 7 Series DDR3/DDR2 - Trace Matching and Derating Guidelines N/A N/A
51475 MIG 7 Series Design Assistant - MIG 7 Series DDR2/DDR3, Board Layout and Design Guidelines N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34204 MIG v3.0-3.3, Virtex-6 DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue N/A N/A
35978 Design Advisory for MIG, MPMC Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs N/A N/A
35976 Design Advisory for MIG, MPMC Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality (software/IP update required) N/A N/A
35818 Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces N/A N/A
36291 MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration N/A N/A
39076 MIG Virtex-6, Spartan-6 FPGA MCB - Disabling the DLL from a Micron memory DIMM N/A N/A
40876 MIG 7 Series v1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications N/A N/A
41981 MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Cntrl Pins Should be Limited to a Single Bank N/A N/A
41752 MIG 7 Series DDR3/DDR2 - Can a x16 interface fit into a single bank? N/A N/A
39549 MIG Virtex-6 DDR2/DDR3 - Read and Write FIFO Depths N/A N/A

Actions

AR# 42024
Date Created 05/03/2011
Last Updated 01/24/2013
Status Active
Type Solution Center
Devices
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
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