MIG 7 Series - Internal/External VREF Guidelines

AR#	42036	Search For Another Answer
Topic	MIG
Last Updated	05/22/2012
Status	Active
Type	Known Issues

Description

The 7 Series FPGAs have the option of supplying the input reference voltage (VREF) through an external voltage source or by using internal VREF.

For 7 Series MIG DDR3 designs, are there a guidelines for when internal VREF or external VREF should be used?

Solution

For DDR3 SDRAM interfaces running at or below 800 Mb/s, users have the option of selecting Internal VREF to save two I/O pins or using external VREF. VREF is required for banks containing DDR3 interface input pins (DQ/DQS).

The 7 Series MIG tool includes an Internal VREF option on the FPGA Options screen. Selecting this option properly sets up the UCF Constraint to enable Internal Vref.

NOTE: VREF is required for inputs only. Therefore, if a MIG pin-out includes a bank with outputs only, that is, Address/Control Groups, the VREF pins can be used for Address/Control signals or GPIO (regardless of internal and external VREF selection).

Additional Information

For External VREF specifications, see the appropriate 7 Series FPGA DC and Switching Characteristics Data Sheet:
http://www.xilinx.com/support/documentation/7_series_data_sheets.htm.

For general VREF, Internal VREF and DCI information, see the 7 Series FPGA SelectIO Resources User Guide(UG471).