The 7 series FPGAs have the option of supplying the input reference voltage (VREF) through an external voltage source or by using internal VREF.
For 7 series MIG DDR3 designs, are there guidelines for when internal VREF or external VREF should be used?
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For DDR3 SDRAM interfaces running at or below 800 Mb/s, users have the option of selecting Internal VREF to save two I/O pins or using external VREF. VREF is required for banks containing DDR3 interface input pins (DQ/DQS).
The 7 Series MIG tool includes an Internal VREF option on the FPGA Options screen. Selecting this option properly sets up the UCF Constraint to enable Internal Vref.
NOTE: VREF is required for inputs only. Therefore, if a MIG pin-out includes a bank with outputs only, that is, Address/Control Groups, the VREF pins can be used for Address/Control signals or GPIO (regardless of internal and external VREF selection).
Additional Information
For External VREF specifications, see the appropriate 7 Series FPGA DC and Switching Characteristics Data Sheet:
http://www.xilinx.com/support/documentation/7_series_data_sheets.htm.
For general VREF, Internal VREF and DCI information, see the 7 Series FPGA SelectIO Resources User Guide(UG471).
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46227 | MIG 7 Series Solution Center - Top Issues | N/A | N/A |
| 51317 | Xilinx MIG Solution Center, MIG 7 Series Design Assistant - Verify pin-out/banking requirements are met | N/A | N/A |
| 51475 | MIG 7 Series Design Assistant - MIG 7 Series DDR2/DDR3, Board Layout and Design Guidelines | N/A | N/A |
| 53811 | MIG 7 Series RLDRAM 3 - Can an x18 interface fit into a single bank? | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 43250 | MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF Constraint is not Applied Across All Memory Banks | N/A | N/A |
| 41227 | MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 | N/A | N/A |
| 40050 | MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 | N/A | N/A |
| 41752 | MIG 7 Series DDR3/DDR2 - Can a x16 interface fit into a single bank? | N/A | N/A |