We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42063

Licensing - Which Xilinx design tools (software) are licensed?


Which Xilinx design tools (software) are licensed?

When is the license checked out?


The following software tools are licensed as indicated in the comments to the right of the application name. 

Licenses are checked out only when an application that needs a license starts to run. 

Most applications will check out and hold this license for as long as the application is open.

Implementation Tool Flow

  • MAP : ISE feature needed
  • PAR : ISE feature needed
  • BitGen : ISE feature needed; will not run on Trial or Hardware Beta, also requires IP Core feature for licensed LogiCORE IP cores
  • NGDBuild : Requires IP Core feature for licensed LogiCORE IP cores

ISE User Interface tools

  • Project Navigator : Validity check only, for ISE software feature; will not hold a design tool license
  • ChipScope Pro Analyzer : ChipScope Pro and ChipScope Pro SIOTK features required for Analyzer (non-enforced for 11.1); design phase in ISE Design Suite 11.2 and later
  • PlanAhead : PlanAhead feature needed (included in all ISE license configurations)
  • Partial Reconfiguration (PR) : PlanAhead tool will check for a PR license feature at startup and enable PR features if a PR license is available.
    The PR feature is also checked-out and immediately checked-in during NGDBUILD for each RP encountered. (It is not held for the duration of NGDBUILD).
  • ISIM : ISIM feature needed
  • CORE Generator : IP Core feature; for generation of licensed LogiCORE IP cores


  • XPS GUI : XPS/SDK license validity check only; will not hold a license
  • PlatGen : XPS feature needed
  • SDK GUI : SDK feature validity check only; will not hold a license (Applicable to ISE 13.4 and earlier)
  • LibGen : SDK feature needed (Applicable to ISE 13.4 and earlier)
  • XST (in EDK) : Generate Netlist requires IP Core feature for synthesis of licensed LogiCORE IP cores


  • System Generator : SysGen feature needed for Generate command
  • AccelDSP : AccelDSP feature needed for Generate step


  • Vivado Synthesis : Requires Synthesis feature
  • Vivado implementation  : Requires Implementation feature
  • Vivado Simulation : Requires Simulation feature
  • Analyzer : Requires Analyzer feature
  • Vivado HLS : Requires HLS feature. Available for Vivado-based flows only

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42062 Licensing - What is Licensed? N/A N/A
AR# 42063
Date Created 10/31/2011
Last Updated 10/03/2014
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • Vivado Design Suite
  • Less