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AR# 42128

FPGA Configuration - How many clock cycles should I apply to CCLK after DONE has gone High?


How many clock cycles should be applied to CCLK after DONE has gone High to ensure that my FPGA device is fully operational?


DONE is released by the Startup sequence to indicate that configuration has completed.

The state is defined in BitGen using the "-g DONE_cycle" option. By default, DONE is released in cycle 4.

DONE indicates that configuration is complete and all data has been loaded, but some extra clock cycles need to be applied to ensure the startup sequence completes correctly.

The startup is controlled by a sequential 7-state machine. A conservative number for the clock cycles required after DONE is 24; this will catch most use cases where there is ideal clock of DONE and default options are used.

Some BitGen options add some extra latency to the startup sequence.

These include:

  • LCK_cycle - delays the startup until all DCM/MMCMs are locked; as a result, the number of clock cycles added is undefined.
  • Match_cycle - delays startup until DCI is matched; as a result, the number of clock cycles added is undefined.
  • DONE_PIPE - adds a clock cycle to the state assigned in DONE_CYCLE.

If you do not clock the startup completely, some of the following symptoms can be observed:

  • I/O remains 3-stated.
  • Dual mode pins operate in LVCMOS rather than the specified I/O standard. If you are using DCI on these Dual Mode pins, your DCI will calibrate for LVCMOS rather than your chosen I/O standard. This can be worked around by referring to (Xilinx Answer 14887)
  • ICAP interface cannot be accessed from the FPGA fabric as the configuration logic is locked.
  • Duty Cycle or swing distortion on some non-dual mode pins; this can be seen on pseudo differential signal such as DIFF_SSTL_15 or differential signal like LVDS, etc.

This will occur if the device has not reached the End of Startup state machine. The device can be fully operational before the device reaches this End of Startup state. This can lead to ICAP read and write failures or dual mode pins not operating in the correct I/O standard.

This event is indicated by the EOS signal being driven High. This can be observed in the STAT register or detected in the FPGA fabric using the STARTUP primitive.

For designs accessing the ICAP, it is good design practice to instantiate the STARTUP primitive.

This primitive has an EOS pin, which will indicate when the configuration process has completed and that the ICAP is available for read and write access.

One exception here is when the JTAG configuration is used. JTAG has top priority access to configuration logic.

If JTAG is accessing configuration logic, then ICAP read and writes will fail. This EOS pin value will not indicate that JTAG has access.

AR# 42128
Date Created 05/11/2011
Last Updated 10/27/2015
Status Active
Type General Article
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