We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42164

7 Series Integrated Block Wrapper v1.1 for PCI Express - Component Switching Limit Error Occurs with x8 gen2 Core when a Virtex-7 -1 Speed Grade Is Targeted


Known Issue: v1.1

The CORE Generator customization GUI for the7 Series Integrated Block Wrapper v1.1 for PCI Express allows users to select an x8 gen 2 core when targeting a Virtex-7 with a -1 speed grade. When running the design through MAP, it results in a Component Switching Limit error on the dedicated Block RAM.

For all 7 Series Integrated Block for PCI Express Known Issues, see (Xilinx Answer 40469).


An x8 Gen 2 (5 GT/s) core requires a -2 or -3 speedgrade targeted Virtex-7. This issue is scheduled to be fixed in the v1.2 ISE 13.3 Design Suite GUI.

Revision History
10/18/2011 - Initial Release

Linked Answer Records

Master Answer Records

AR# 42164
Date 05/20/2012
Status Active
Type Known Issues
Page Bookmarked