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AR# 42228

13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design


It has been seen in some designs that including ChipScope designs andreading the NGC cores into XST can cause XST to perform some optimizations which cause the addition of BUFG's to local clock signals which do not require them. This is seen in cases where the clock signals in question are not being used by the ChipScope blocks and as such are independent of the ChipScope logic.


It is possible to work around this in the following ways:
  1. Switch off the "read_cores" property in XST
  2. Set attribute of BUFFER_TYPE = NONE in the HDL for the clock signals in question.

AR# 42228
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 13.1
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