In multiplexed address mode, the address can be provided to the RLDRAM in two parts with two consecutive rising clock edges. This provides the advantage of reducing the number of address pins required to a maximum of 11 bits. However, MIG v3.7 does not reduce the address width when using Address Mux = Multiplexed.
This is incorrect as MIG should be reducing the number of address bits when Address Multiplexing is used.
Customers can work around the problem by first generating the MIG design and then by making the following modifications:
1. Modify the ADDR_WIDTH parameter in the top-level design file.
2. Open rld_phy_write_control_io.v and replace the following:
Replace Lines 150-156 with:
generate
if (ADDR_WIDTH>11) begin : ADDR0_X_12_18
assign addr0_x[12:11] = 'b0;
assign addr0_x[14:13] = addr0[14:13];
assign addr0_x[16:15] = 'b0;
assign addr0_x[18:17] = addr0[18:17];
end
if (ADDR_WIDTH>19) begin : ADDR0_X_19
Replace Lines 192-199 with:
generate
if (ADDR_WIDTH>11) begin : ADDR0_Y_12_18
assign addr0_y[12:11]= 'b0;
assign addr0_y[14:13]= addr0[12:11];
assign addr0_y[16:15]= 'b0;
assign addr0_y[17] = addr0[16];
assign addr0_y[18] = addr0[15];
end
if (ADDR_WIDTH>19) begin : ADDR0_Y_19
The address width has been fixed in the ISE 13.2 MIG v3.8 release, but simulations will still fail as the rld_phy_write_control_io modifications are still required. The modifications to rld_phy_write_control_io.v will be fixed in the ISE 13.3 release.