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AR# 42236

14.x Timing - DSP48 component delay is too large to meet the setup timing requirement

Description

A path going through DSP48 does not meet the setup timing requirement because the DSP48 component delay is too large.

The setup timing requirement is 5.4 ns:

SLICE_X43Y59.CQTcko0 0.45 ns
DSP48_X1Y24.B0 net (fanout 2) 0.501 ns
DSP48_X1Y24.P7 Tdspdo_BP_M3.646 ns
SLICE_X45Y61.B6 net (fanout 1) 0.497 ns

Howcan Iresolve this issue?

Solution

The DSP48 component delay (Tdspdo_BP_M) is large because the pipeline registers within the DSP48 are not used. So, there are only pure combinational logic in the DSP48 which results in the large component delay.

To resolve this problem, add pipeline stages if you use the CORE Generator tool to generate the DSP48 core, or make use of the pipeline registers if you instantiate the DSP48 primitive in your design.

AR# 42236
Date Created 04/30/2012
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
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