UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42258

MIG 7 Series RLDRAMII - Can an x18 interface fit in a single bank?

Description

When generating an x18 RLDRAMII interface through MIG, is it possible to fit an x18 RLDRAM interface into a single bank?

Solution

Yes, it is possible. Follow the steps below to achieve this:

  1. Remove the QVLD pins - QVLD is not used in the design.
     
  2. Disable Data Mask (DM) - The Data Mask can be disabled through the MIG 7 Series tool for designs not requiring the ability to mask data (tie the pins low on the board).
     
  3. Use Address Multiplexing Mode - Address Multiplexing mode reduces the address pin count from 20-22 bits down to 11 and will free up an extra byte lane in the Address/Control Bank. 
     
  4. Use Internal Vref; this allows the Vref pins to be used as GPIO, freeing up two pins per bank where inputs are used.
AR# 42258
Date Created 05/20/2011
Last Updated 08/13/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
IP
  • MIG