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# AR# 42299

## Description

In the Timing Report, detailed section of a given timing path, the Logic to Route ratio is larger than 50%. Why?

## Solution

The path delay is a combination of Wire Delay + Pin Delay + Component Delay. The Wire Delay is the delay from the output pin when it comes out of the primitive to the input pin of the destination Slice. This does not include the Pin delay, which is the extra delay from the pin of the slice to the input pin of the primitive. In previous versions of the tools we used to lump the Pin Delay and Component Delay into one sum as Component Delay, and then report a delay for the wire only. Each input pin of the primitive typically had a the same delay. Then, when we used this method, the logic versus route calculation looked like a 50/50 ratio and that was thought to be an acceptable routed path with even distribution of delay.

With the newer devices it has become very difficult follow this method. As we have expanded the number of primitives (LUT4 to LUT6), the number of input pins in the slice has also increased. Thiswould require a unique model for each component to show the Pin Delay + Component Delay. So, the model was changed to be (Wire Delay + Pin Delay) + Component Delay. Reducing the size of the database needed to move the Pin Delay to the Wire Delay reduced the runtime. This moved a lot of the actual delay from the Component to the Wire Delay (Wire Delay = Pin Delay + Wire Delay) DuringPlace and Routethe tools will also swap and push the most critical net to the fastest pin. If the failed path uses a slow pin, its because another path required the fastest pin delay, and so you will see an increase in route delay and skewed ratio. If the path uses input pin A4 to A1, the ratio will look worse. For asix level path this will result in a worse case 2.130 ns of extra route delay.

Since the Component Delay is now a very small component of the delay, more levels of logic in the path will increase the route percentage and make the Route to Logic ratio much higher. For Virtex-6 FPGA paths with a ratio of 20% to 35% Component Delay is typical.
AR# 42299
Date 12/15/2012
Status Active
Type General Article
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