UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42309

MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Postponing and Pulling-in REFRESH command

Description

The DDR3 JEDEC specification requires refresh cycles at an average periodic interval of tREFI, but to allow improved efficiency up to 8 refresh commands can be postponed or pulled-in to delay or reduce the number of refresh commands sent later. For more information on postponing and pulling-in refresh commands, refer to the DDR3 JEDEC specifications.

Note: This Answer Record is part of the Xilinx MIG Solution Center(Xilinx Answer 34243) Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

MIG supports the pulled-in refresh feature of DDR3 for Virtex-6 and 7 series FPGA designs, and generates up to 8 pulled-in refresh commands when the rank is not busy. When the rank is active, the refresh commands are sent on their periodic cycles as defined by the tREFI interval. Pulling-in refresh commands when the RANK is not active improves bus efficiency during normal operation.

Linked Answer Records

Master Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34371 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Auto-Refresh Counter (Refresh Period) N/A N/A
AR# 42309
Date Created 05/25/2011
Last Updated 09/18/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-7
  • Artix-7
  • Kintex-7
  • Less
IP
  • MIG
  • MIG 7 Series