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AR# 42320 MIG v3.7 Virtex-6 and MIG 7 Series v1.1, DDR3 RDIMM - Incorrect Column Address Width

Description

According to the DDR3 JEDEC specifications for x8 devices, if Row Address Width is 15 bits, Column Address Width has to be 10 bits. MIG v3.7 and MIG 7 Series v1.1 sets the Column Address Width to 11 for the MT9JSF12872PY-1G1 and the MT9JSF25672PZ-1G4, which is incorrect.

Solution

This issue only affects the MT9JSF12872PY-1G1 and the MT9JSF25672PZ-1G4 and is fixed in MIG v3.8 for Virtex-6 FPGA and MIG 7 Series v1.2.

You can also work around this issue by changing the COL_WIDTH parameter value from 11 to 10 in the top-level module in the MIG generated design, that is, example_top, user_design_top, sim_tb_top and the .veo/.vhdo files, if used.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Actions

AR# 42320
Date Created 05/26/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
IP
  • MIG
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