This error can occur when using a Verilog Testbench with a design written in VHDL, and VHDL type hierarchical boundary references are used in the Verilog testbench.
An example of this is below:
In this example, RefClk is within the UUT instance of the VHDL file, but is not an output port.
The problem occurs because Verilog does not have the ability to access signals in lower levels of hierarchy.
To work around the problem in this case, bring any signals out from the test files to the testbench via ports.