For asynchronous links, meaning that each link partner is clocked by a different oscillator, the recommended value for PMA_RX_CFG is 25'h05CE049. Set this value in the file called gtpa1_dual_tile_wrapper.v[hd] in the generated core's source directory.For more information regarding clocking and PCI Express, see (Xilinx Answer 18329).
Revision History
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 42569 | Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3 | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45702 | Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions | N/A | N/A |