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AR# 42366

13.1 Timing Analyzer/Trce - Virtex-6 - Paths to write enable ports of RAMB18E1 are increased

Description

When I run the Timing Analyzer in ISE13.1, I found an increase in the number of analyzed paths associated with RAMB18E1 components.

Solution

In previous versions of ISE software, Timing Analyzer analysismissed some of the paths to the RAMB18E1 component. Thefollowing pinswere not analyzed:

[RAM_MODE=SDP]
WEBWE[7:4]

[RAM_MODE=TDP]
WEA[3:2]

This only affectsVirtex-6 FPGAdesigns that areusing the RAMB18E1.
AR# 42366
Date Created 06/16/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4